Advances in semi-conductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, the power demands of integrated circuits, such as microprocessors, have drastically increased. Typically there have been two approaches to handling this voltage supply degradation. In one post-design scenario, a large amount of decoupling capacitors are added to a processor package and/or motherboard to reduce voltage droops. Yet, adding capacitors is both monetarily expensive (extra money per capacitor) and physically expensive (the capacitors take up additional critical signal routing/placement space). In a second, pre-design scenario, processor designers take into account the voltage supply issues by adding a guard-band (a tolerance band that the processor still operates appropriately). However, an increase in guard-band both results in an additional power losses and performance degradation, since the designers are constrained by designing to worst case scenarios.
As one example of such a worst case scenario, input/output (I/O) patterns that cause resonant frequencies on I/O interfaces potentially cause noise in an associated power delivery network. In fact, as the I/O speeds of devices increases, power delivery noise targets shrink, accordingly. And as the power delivery noise targets decrease, the need for more on-die decoupling capacitors increase, which results in even more expense. Unfortunately, current scramblers only provide random pattern scrambling without consideration of a patterns affect on a power delivery network.